1. Field of the Invention
This invention relates to an electronic circuit, and more particularly to an electronic circuit for converting asynchronous pulses into synchronous pulses.
2. Description of Related Art
Digital data processing devices and digital communications equipment, to mention only a few examples, often must receive asynchronous digital information. Generally, the receiving device must clock or strobe the asynchronous information into an input register. This information generally is a series of high voltage states and low voltage states (i.e., logical "1" and logical "0" states). The duration of each logical "1" state and each logical "0" state is typically unknown. Therefore, a problem exists in determining when transitions occur in the incoming data stream. Incoming data generally cannot be interpreted if the transitions from logical "1" state to logical "0" state and back again cannot be accurately determined.
In one common scheme for receiving asynchronous digital data, an internal clock that has a much greater frequency than the incoming data stream is used to "sample" the incoming data stream. On each rising edge of the internal clock, the data is clocked into an input register. Since the clock frequency is relatively high with respect to the incoming data, there is no chance that data will transition from one state to another before two sequentially rising edges of the internal clock occur.
Two limitations exist in such a system. First, under the limits of the Nyquist criterion, the frequency of such an internal clock must be at least twice the incoming signal frequency. Second, an incoming signal must not have a pulse width (either logical "1" state or logical "0" state) that is less than one full cycle of the internal clock.
These limitations have been overcome in part by a data sampling architecture disclosed in U.S. Pat. No. 4,935,942 to Hwang et al. FIG. 1 shows the Hwang pulse synchronizer. The input signal RD/WR is coupled to the clock input of a first standard D-type rising edge triggered flip-flop 40. Four other flip-flops 42, 44, 46, 48 are coupled to the output of the first flip-flop 40 as a synchronizer 59, which synchronizes the incoming signal to two internal clocks A, B. Two additional flip-flops 50, 54 coupled to two AND gates 52, 56 and an OR gate 58 shape the output of the flip-flops 46, 48. The synchronizer may be reset only by a reset input at the first flip-flop 40. The input signal can have a frequency up to about 90% of the frequency of the internal clock A, B.
A continuing goal of integrated circuit designers is to place more functions on a single substrate. Because area on a substrate is limited, it is important to reduce the number of devices that are used for any particular function. Additionally, the less components used, the higher the reliability of the entire system due to a reduction in the number of points of failure. While the Hwang circuit is effective, it is complex and requires at least two synchronized internal clocks. In addition, extraneous pulses can be generated by noise that triggers the flip-flops of the synchronizer 60. Pulses can also be created upon initial introduction of power to the synchronizer 60. Pulses can also be created upon initial introduction of power to the synchronizer, depending upon how the flip-flops that comprise the synchronizer are initially resolved.
Therefore, it is desirable to synchronize and shape incoming asynchronous data pulses with a less complex (fewer components) and less expensive circuit that requires only one internal clock having a frequency which is only slightly greater than the frequency of the input signal, and in which each flip-flop can be reset independently to guaranty that additional pulses never occur.